三位元加法器 結構模式

module top;
wire Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3;
system_clock #6400 clock1(Cin);
system_clock #3200 clock1(A3);
system_clock #1600 clock1(B3);
system_clock #800  clock1(A2);
system_clock #400  clock1(B2);
system_clock #200  clock2(A1);
system_clock #100  clock3(B1);
adder1 M1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
endmodule

module adder1(Cin,A1,B1,A2,B2,A3,B3,Cout1,Cout2,Cout3,Sum1,Sum2,Sum3);
output Cout1,Sum1,Cout2,Cout3,Sum2,Sum3;
input A1,B1,A2,B2,A3,B3,Cin;
and I1  (A1andB1, A1, B1);
xor I2  (A1xorB1, A1, B1);
and I3  (And1, A1xorB1, Cin);
 or I4  (Cout1, A1andB1, And1);
xor I5  (Sum1, A1xorB1, Cin);

and I6   (A2andB2, A2, B2);
xor I7   (A2xorB2, A2, B2);
and I8   (And2, A2xorB2, Cout1);
 or I9    (Cout2, A2andB2, And2);
xor I10 (Sum2, A2xorB2, Cout1);


and I11 (A3andB3, A3, B3);
xor I12 (A3xorB3, A3, B2);
and I13 (And3, A3xorB3, Cout2);
 or I14 (Cout3, A3andB3, And3);
xor I15 (Sum3, A3xorB3, Cout2);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>100000)$stop;
endmodule

三位元全加法器 行為模式

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

一位元全加法器-2

module top;

wire A, B, Cin, c1, c2, c3, sum, Cout;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);

xor(c1, A, B);
and(c2, A, B);
xor(sum, c1, Cin);
and(c3, c1, Cin);
xor(Cout, c3, Cin);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

一位元全加法器

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_in!= 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_in!= 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_in != 1 | sum !== 0)
                $display(" 0+1+1=10 sum is WRONG!");
              else
                $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_in!= 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
     carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_in != 1 | sum !== 0)
                $display(" 1+0+1=10 sum is WRONG!");
              else
                $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_in != 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_in != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(a&b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

11/4 課堂實作

11/4 課堂實作