12/23(三) 期末上機考-NOR

module top;

wire A, B, C, D,NA,NB,NC,ND, NF, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor S1(NA, A, A);
nor S2(NB, B, B);
nor S3(NC, C, C);
nor S4(ND, D, D);

nor C1(F1,A,B,C);
nor C2(F2,A,NB,ND);
nor C3(F3,NA,NB,NC,D);
nor C4(F4,NA,B,NC);

nor o1(NF,F4,F2,F3,F1);
nor o2(F ,NF,NF);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

12/2 課堂實作-期末上機考模擬(第一個)

module top;

wire A, B, C, D, NA, NB, NC, ND, F1, F2, F3, F4, F;
system_clock #800 clock1(A);
system_clock #600 clock2(B);
system_clock #400 clock2(C);
system_clock #200 clock2(D);
not a1(OUT, NA, A);
not a2(OUT, NB, B);
not a3(OUT, NC, C);
not a4(OUT, ND, D);

and a5(F4,  A,  NC, ND);
and a6(F2, NA,  NB,  D);
and a7(F3,  B,  NC, ND);
and a8(F1,  C,  D     );

or  a9(F,F1,F2,F3,F4);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>10000)$stop;

endmodule