12/23(三) 期末上機考-NOR

module top;

wire A, B, C, D,NA,NB,NC,ND, NF, F, F1, F2, F3, F4;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor S1(NA, A, A);
nor S2(NB, B, B);
nor S3(NC, C, C);
nor S4(ND, D, D);

nor C1(F1,A,B,C);
nor C2(F2,A,NB,ND);
nor C3(F3,NA,NB,NC,D);
nor C4(F4,NA,B,NC);

nor o1(NF,F4,F2,F3,F1);
nor o2(F ,NF,NF);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule